The present invention is directed to a method for controlling the data transmission between a central unit and a communication controller with an intervening microprocessor controlled central unit interfacing control circuit having respective interface circuits for the communication controller and the central unit, and is directed to a circuit arrangement for the implementation of the method.
In the data transmission between a central unit and a communication controller or data transmission processor, a microprocessor-controlled central unit that interfaces the control circuits are utilized in order to optimally quickly accept and execute central unit instructions (for example, read, write) that are output via a channel interface of the central unit to the central unit interfacing control circuit. The firmware of the microprocessor unit controlling the central unit interfacing control circuit not only controls the central unit channel interface but also controls the interface to the communication controller. Since the central unit has highest priority, the firmware of the microprocessor unit of the central unit interfacing control circuit must, if at all possible, react immediately to the central unit requests. The firmware of the microprocessor unit frequently experiences interruptions that are completely asynchronous relative to the ongoing instruction executions in order to control the operational sequences at the central unit channel interface. A problem is that there are firmware sequences that are not allowed to be interrupted. When the central unit operates with a plurality of device addresses quasi-simultaneously, time-consuming address switching events must additionally be continuously controlled by the firmware of the microprocessor unit. When it is necessary that the central unit be operated under real time conditions, the firmware gets into more and more difficulty handling both interfaces with adequate speed. The channel interface of the central unit is occupied longer than necessary and as a result is not usable for additionally connected periphery equipment.
PCT Application WO 86/05293 discloses a microprocessor-controlled central unit interfacing control circuit that provides data transmission from a central unit to a plurality of different periphery equipment. It has an input circuit portion connected to the central channel interface and has two output circuit portions where one controls the data exchange with a printer means and the other controls the data exchange with at least one tape recorder means. The input circuit portion is allocated to one of the output circuit portions. If both output circuit portions wish to simultaneously access the input circuit portions, a referee means decides which output circuit the input circuit is allocated to. In this case, the data transmission can only be implemented with a delay. A data transmission in burst mode is thereby possible. The goal of the known central unit interfacing control circuit is to execute a data transmission between a central unit and a plurality of periphery equipment with optimally few central unit interruptions.
In addition to central unit interfacing control circuits, sequential logical systems are also known in the prior art (see Tietze/Schenk, Halbleiterschaltungstechnik, 4th Edition, 1978, Springer-Verlag, page 457). Sequential logic systems are thereby composed of a combinatorial portion, a combinational logic system, and of a status memory in which the system status is stored for a time clock. The new system status depends on the old system and on the input variables.
The output variables of the sequential logic system depend on the input variables thereof and on the old system status. The sequence of the system statuses can be defined by the selection of the input variables and of the old system status.